The present invention relates to data center infrastructure, and more particularly, this invention relates to high speed look-up using look-up rules cached based on flow heuristics.
Every network packet processor for Layer-2 and/or Layer-3 switches requires one or more look-up tables in order to discover a set of operations to be performed on the packets received from other devices in the network. Look-up tables hold specific information, such as IPv4 Routing Tables, IPv6 Routing Tables, Address Resolution Protocol (ARP) Tables, Media Access Control (MAC) Tables, Access Control List (ACL) Tables, Host Specific Routes Tables, etc. Scaling of such look-up tables is critical in order to allow for the scaling of packet processor chipsets used in devices which rely on these look-up tables. Larger Ternary Content-Addressable Memory (TCAM) banks may solve the problem of scaling the number of look-up entries or the size of the look-up table. However, one problem with this approach is that line rate look-up is complex to solve.
As the packet processor bandwidth increases, the look-up speed should increase similarly. For example, an Ethernet packet processor with 960 Gbps of switching bandwidth should have a successful look-up speed of 1440 Million successful searches per second (MSPS). As the packet processor adds more new features, the search process adds more numbers of parameters or tuples for the search, and thus the search becomes more complex. Switching processors, such as Application Specific Integrated Circuits (ASICs) have limits of on-chip look-up memories. As the look-up table size increases, the chip size, complexity, and size also needs to increase. Therefore, most of the highly scaled up switching ASICs provide external expansion of look-up tables. This necessitates more high speed TCAMs with wider and faster interface connectivity. However, this adds significant cost to the overall device employing the switching ASIC and also complicates board designs using such switching ASICs.
Accordingly, it would be beneficial to have a solution which enables high speed look-up without requiring extensive increases in the computing capacity of switching processors or more high speed TCAMs.